The fabrication of an integrated circuit normally begins by processing the semiconductor substrate to divide the surface area into regions where active devices and interconnects are to be formed, and other regions of dielectric which electrically isolate the active device regions. Shallow trench isolation (STI) structure is a common electrical isolation technique, especially for a semiconductor chip with high integration. The conventional STI process starts by forming a pad oxide layer and a nitride layer over a substrate surface. The pad oxide and nitride layer are patterned using conventional photolithographic techniques to form an opening over the area where the isolation structure is to be formed. Next, a relatively shallow trench is typically dry etched into a silicon (or other semiconductor) substrate. Dry etching may be performed by way of a plasma or reactive ion etch (RIE). Typically, in a plasma etching process, an etchant source gas is supplied to an etching chamber where the plasma is formed to generate ions from the etchant source gas. Ions are then accelerated towards the process wafer surface, by a bias voltage, where they impact and remove material (etch) from the wafer. Various gas chemistries are used to provide variable etching rates for etching different materials. Frequently used dry etchant source gases include fluoro-hydrocarbons to etch through a metal nitride layer, for example silicon nitride (SiN), and chlorine (Cl2), and HBr to etch through a silicon layer to form the etched shallow trench isolation (STI) structure. Subsequently, the trench is filled with an insulator material such as silicon dioxide, for example, by a high density plasma chemical vapor deposition (HDP-CVD) or other process. Typically, the nitride and pad oxide layers are removed, for example by chemical mechanical polishing (CMP) or other techniques to complete the STI structure.
U.S. Pat. Nos. 5,731,241, and 6,562,696 describe additional issues associated with shallow trench isolation devices. One issue is related to the acid etch back process for removal of the nitride layer. Typically, acidic etching creates damage to the STI features, such as sharp corners, which can create localized high electrical fields, leading to shorts, yield losses and isolation reliability concerns.
U.S. Pat. Nos. 5,915,192 and 6,232,202 are incorporated by reference herein in their entireties, as though fully set forth herein. These patents describe the formation of retrograde STI structures using isotropic etching to produce a trench having a first portion, a second portion and walls, the second portion of the trench having a larger dimension than the first portion. These trenches are subsequently filled with dielectric material to provide isolation properties. The resultant retrograde STI structure increases the electrical insulation between the devices while maintaining the layout of the device on the substrate.
Based on market demands, there continues to be an increasing need for higher density devices. As spacing between circuit devices, such as transistors, on a given semiconductor substrate surface becomes increasingly smaller, the need for more effective isolation from defects, such as leakage currents, is required for reliability.